German Published Patent Application No. 10 2007 048 604 describes an MEMS wafer having a layered structure, in which a micromechanical structure is produced using processes of surface micromechanics.
In practice, initially a first insulating layer is applied to a semiconductor substrate for this purpose. A printed conductor level in the form of a doped and structured polysilicon layer is produced above this insulating layer. Finally, a comparatively thick epipolysilicon layer, in which the micromechanical structure of the MEMS element is implemented, is deposited as the functional layer above a further insulating layer, which is additionally used as a sacrificial layer. For this purpose, the functional layer is initially structured in order to define the geometry of the micromechanical structure. The micromechanical structure is then exposed in a sacrificial layer process, during which the further insulating layer below the micromechanical structure is removed.
An ASIC wafer is mounted on the layered structure of the MEMS wafer thus processed, specifically face down, in such a way that the surface of the ASIC wafer provided with circuit functions faces toward the MEMS wafer. In this way, both the micromechanical structure of the MEMS element and also the circuit functions of the ASIC element are capped. The connection between the MEMS wafer and the ASIC wafer is established here in a eutectic bonding process. In addition to a hermetically sealed connection between the two wafers, electrical connections may also be established between the MEMS wafer and the ASIC wafer.
The known component concept allows cost-effective mass production of robust components having a micromechanical sensor or actuator function and an evaluation or activation circuit, since here not only the individual component parts—the MEMS element and the ASIC element—are manufactured in the wafer composite, but rather also their assembly is implemented to form a component on the wafer level. The MEMS functions and the ASIC functions may be tested on the wafer level, and even the calibration of the individual components may take place on the wafer level. The stacked structure of the known components additionally contributes to a reduction of the manufacturing costs of the terminal equipment, since these components only require a comparatively small mounting area during the second level assembly.